A method for designing a circuit. The method may include obtaining a register-transfer level (RTL) file for an integrated circuit. The method may further include generating, using an RTL-synthesis compiler and from the RTL file, a gate-level netlist including a plurality of cells assigned to a plurality of cell groups. The method may further include obtaining, from a user, a selection of a user-defined criterion and a selected cell group from the plurality of cell groups. The method may further include partitioning the selected cell group into a first partitioned cell group including a first subset of the plurality of cells and a second partitioned cell group comprising a second subset of the plurality of cells. The method may further include generating a floorplan comprising the first partitioned cell group and the second partitioned cell group.