Invention Grant
- Patent Title: Negative capacitance matching in gate electrode structures
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Application No.: US16167081Application Date: 2018-10-22
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Publication No.: US10332969B2Publication Date: 2019-06-25
- Inventor: Rohit Galatage , Steven Bentley , Puneet Harischandra Suvarna , Zoran Krivokapic
- Applicant: GLOBALFOUNDRIES Inc.
- Applicant Address: KY Grand Cayman
- Assignee: GLOBALFOUNDRIES Inc.
- Current Assignee: GLOBALFOUNDRIES Inc.
- Current Assignee Address: KY Grand Cayman
- Agency: Amerson Law Firm, PLLC
- Main IPC: H01L29/423
- IPC: H01L29/423 ; H01L29/66 ; H01L21/28 ; H01L29/78 ; H01L29/788

Abstract:
A semiconductor device includes a gate electrode structure that is positioned adjacent to a channel region of a transistor element. The gate electrode structure includes a floating gate electrode portion, a negative capacitor portion, and a ferroelectric material capacitively coupling the floating gate electrode portion to the negative capacitor portion. A first conductive material is positioned between the floating gate electrode portion and the ferroelectric material, wherein a first portion of the first conductive material is embedded in and laterally surrounded by the floating gate electrode portion, and a second conductive material is positioned between the first portion of the first conductive material and the ferroelectric material, wherein the second conductive material is embedded in and laterally surrounded by a second portion of the first conductive material.
Public/Granted literature
- US20190115437A1 NEGATIVE CAPACITANCE MATCHING IN GATE ELECTRODE STRUCTURES Public/Granted day:2019-04-18
Information query
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