Timing exact design conversions from FPGA to ASIC

Invention Grant

US10339245B2 Timing exact design conversions from FPGA to ASIC 有权

Please log in to see more content

Patent Title: Timing exact design conversions from FPGA to ASIC
Application No.: US15407242

Application Date: 2017-01-16
Publication No.: US10339245B2

Publication Date: 2019-07-02
Inventor: Raminda Udaya Madurawe
Applicant: CALLAHAN CELLULAR L.L.C.
Applicant Address: US DE Wilmington
Assignee: CALLAHAN CELLULAR L.L.C.
Current Assignee: CALLAHAN CELLULAR L.L.C.
Current Assignee Address: US DE Wilmington
Main IPC: G06F17/50
IPC: G06F17/50 ; H03K19/177 ; H01L27/105 ; G11C16/04 ; G11C17/16

Timing exact design conversions from FPGA to ASIC

Abstract:

A device having a design conversion from a field programmable gate array (FPGA) to an application specific integrated circuit (ASIC), comprising: a user configurable element in the FPGA replaced by a mask configurable element in the ASIC, wherein the FPGA and the ASIC have identical die size and identical transistor layouts.

Public/Granted literature

US20170124241A1 TIMING EXACT DESIGN CONVERSIONS FROM FPGA TO ASIC Public/Granted day:2017-05-04

Information query

Espacenet