- 专利标题: Memory devices and methods for managing error regions
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申请号: US15927679申请日: 2018-03-21
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公开(公告)号: US10347356B2公开(公告)日: 2019-07-09
- 发明人: Joe M. Jeddeloh
- 申请人: Micron Technology, Inc.
- 申请人地址: US ID Boise
- 专利权人: Micron Technology, Inc.
- 当前专利权人: Micron Technology, Inc.
- 当前专利权人地址: US ID Boise
- 代理机构: Schwegman Lundberg & Woessner, P.A.
- 主分类号: H03M13/05
- IPC分类号: H03M13/05 ; G06F12/02 ; G11C29/12 ; G11C29/44 ; G11C29/00 ; H01L25/18 ; H01L27/108 ; G11C5/04 ; H01L27/06 ; H01L27/105
摘要:
Memory devices and methods are described that include a stack of memory dies and a logic die. Method and devices described include those that provide for repartitioning the stack of memory dies and storing the new partitions in a memory map. Repartitioning in selected configurations allows portions of memory to be removed from use without affecting the rest of the memory device. Additional devices, systems, and methods are disclosed.
公开/授权文献
- US20180374557A1 MEMORY DEVICES AND METHODS FOR MANAGING ERROR REGIONS 公开/授权日:2018-12-27
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