Invention Grant
- Patent Title: Double-gate vertical transistor semiconductor device
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Application No.: US15835703Application Date: 2017-12-08
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Publication No.: US10355128B2Publication Date: 2019-07-16
- Inventor: Praveen Raghavan , Odysseas Zografos
- Applicant: IMEC VZW , Katholieke Universiteit Leuven, KU LEUVEN R&D
- Applicant Address: BE Leuven BE Leuven
- Assignee: IMEC VZW,KATHOLIEKE UNIVERSITEIT LEUVEN, KU LEUVEN R&D
- Current Assignee: IMEC VZW,KATHOLIEKE UNIVERSITEIT LEUVEN, KU LEUVEN R&D
- Current Assignee Address: BE Leuven BE Leuven
- Agency: McDonnell Boehnen Hulbert & Berghoff LLP
- Priority: EP16205495 20161220
- Main IPC: H01L29/78
- IPC: H01L29/78 ; H01L29/66 ; H01L21/8234

Abstract:
A semiconductor device is disclosed that includes a substrate and at least a first, second, third, and fourth vertical transistor supported by the substrate. Each transistor comprises a vertical channel, a polarity gate electrode forming a polarity gate adapted to act on a first portion of the channel to affect a polarity of the channel, and a control gate electrode forming a control gate adapted to act on a second portion of the channel to control the electrical conductivity of the channel. The polarity gate electrode and the control gate electrode of each one of the transistors extend laterally from their respective gate and in mutually opposite directions, and the transistors are laterally spaced from each other and arranged such that the control gate electrodes of the first and third transistor face each other and the control gate electrodes of the second and fourth transistor face each other.
Public/Granted literature
- US20180175193A1 Double-Gate Vertical Transistor Semiconductor Device Public/Granted day:2018-06-21
Information query
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