A superscalar processor, for out of order self-timed execution, comprising a plurality of independent self-timed function units, having corresponding instruction queues for holding instructions to be executed by the function unit. The processor further comprising an instruction dispatcher configured for inputting instructions in program counter order; and determining an appropriate function unit for execution of the instruction and a resource management unit configured for monitoring the function units and signaling availability of the appropriate function unit, wherein the dispatcher only dispatches the instruction to the appropriate function unit in response to the availability signal from the resource management unit.