Invention Grant
- Patent Title: Logic layout with reduced area and method of making the same
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Application No.: US15829459Application Date: 2017-12-01
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Publication No.: US10373942B2Publication Date: 2019-08-06
- Inventor: Ram Asra , Mohit Bajaj , Edward Nowak , Kota V. R. M. Murali
- Applicant: GLOBALFOUNDRIES Inc.
- Applicant Address: KY Grand Cayman
- Assignee: GLOBALFOUNDRIES INC.
- Current Assignee: GLOBALFOUNDRIES INC.
- Current Assignee Address: KY Grand Cayman
- Agency: Ditthavong & Steiner, P. C.
- Main IPC: H01L29/66
- IPC: H01L29/66 ; H01L27/02 ; H01L29/78 ; H01L27/11 ; H01L29/06 ; H01L27/092 ; H01L27/12 ; H01L21/8238 ; H01L29/423
Abstract:
A method of forming a SRAM semiconductor device with reduced area layout and a resulting device are provided. Embodiments include forming a first field effect transistor (FET) over a substrate; forming an insulating material over the first FET; forming a second FET over the insulating material; and patterning the first FET, insulating material and second FET to form fins over the substrate.
Public/Granted literature
- US20190172822A1 LOGIC LAYOUT WITH REDUCED AREA AND METHOD OF MAKING THE SAME Public/Granted day:2019-06-06
Information query
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