- 专利标题: Quadrature clock generating mechanism of communication system transmitter
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申请号: US15717919申请日: 2017-09-27
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公开(公告)号: US10374588B2公开(公告)日: 2019-08-06
- 发明人: Po-Chun Huang , Chao-Ching Hung , Yu-Li Hsueh , Pang-Ning Chen
- 申请人: MEDIATEK INC.
- 申请人地址: TW Hsin-Chu
- 专利权人: MEDIATEK INC.
- 当前专利权人: MEDIATEK INC.
- 当前专利权人地址: TW Hsin-Chu
- 代理商 Winston Hsu
- 主分类号: H03K5/12
- IPC分类号: H03K5/12 ; H03K5/15 ; H03K21/02 ; H04B1/04
摘要:
A quadrature clock generating apparatus connected to a local oscillator generating an input clock signal and an inverted input clock signal includes a fractional dividing circuit and a quadrature signal generating circuit. The fractional dividing circuit is configured for receiving the input clock signal and the inverted input clock signal, and for performing frequency-division upon the input clock signal and the inverted input clock signal to generate a frequency-divided clock signal according to a fractional dividing parameter. The quadrature signal generating circuit is configured for receiving the input clock signal, the inverted input clock signal, and the frequency-divided clock signal to generate a plurality of quadrature clock signals.
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