Invention Grant
- Patent Title: Quadrature clock generating mechanism of communication system transmitter
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Application No.: US15717919Application Date: 2017-09-27
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Publication No.: US10374588B2Publication Date: 2019-08-06
- Inventor: Po-Chun Huang , Chao-Ching Hung , Yu-Li Hsueh , Pang-Ning Chen
- Applicant: MEDIATEK INC.
- Applicant Address: TW Hsin-Chu
- Assignee: MEDIATEK INC.
- Current Assignee: MEDIATEK INC.
- Current Assignee Address: TW Hsin-Chu
- Agent Winston Hsu
- Main IPC: H03K5/12
- IPC: H03K5/12 ; H03K5/15 ; H03K21/02 ; H04B1/04

Abstract:
A quadrature clock generating apparatus connected to a local oscillator generating an input clock signal and an inverted input clock signal includes a fractional dividing circuit and a quadrature signal generating circuit. The fractional dividing circuit is configured for receiving the input clock signal and the inverted input clock signal, and for performing frequency-division upon the input clock signal and the inverted input clock signal to generate a frequency-divided clock signal according to a fractional dividing parameter. The quadrature signal generating circuit is configured for receiving the input clock signal, the inverted input clock signal, and the frequency-divided clock signal to generate a plurality of quadrature clock signals.
Public/Granted literature
- US20180123575A1 QUADRATURE CLOCK GENERATING MECHANISM OF COMMUNICATION SYSTEM TRANSMITTER Public/Granted day:2018-05-03
Information query
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