An array substrate is provided, which includes: a base substrate; a plurality of gate lines, a plurality of data lines and a plurality of common electrode lines arranged on the base substrate; a pixel electrode arranged at each region defined by adjacent gate lines and adjacent data lines; and a TFT arranged at a position in proximity to a junction between each of the gate lines and the corresponding data line. A drain electrode of the TFT is electrically connected to the pixel electrode through a via-hole. Each common electrode line includes a primary electrode line extending in a direction identical to an extension direction of the gate line, and a secondary electrode line connected vertically to the primary electrode line. The secondary electrode line includes at least one first secondary electrode line arranged between the via-hole and the data line.