- Patent Title: Apparatus and methods for via connection with reduced via currents
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Application No.: US16192673Application Date: 2018-11-15
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Publication No.: US10383298B2Publication Date: 2019-08-20
- Inventor: Atsushi Morishima
- Applicant: MICRON TECHNOLOGY, INC.
- Applicant Address: US ID Boise
- Assignee: Micron Technology, Inc.
- Current Assignee: Micron Technology, Inc.
- Current Assignee Address: US ID Boise
- Agency: Dorsey & Whitney LLP
- Main IPC: A01H5/10
- IPC: A01H5/10 ; H05K1/11 ; H05K1/02 ; H05K1/18 ; A01H6/54 ; A01H1/02 ; C12N15/82

Abstract:
Apparatuses and methods including conductive vias of a printed circuit board are described. An example apparatus includes a first layer including a first conductive plate; a component on the first layer, a second layer including a second conductive plate that may be coupled to an external power source; a third layer between the first layer and the second layer, the third layer including a third conductive plate; a first via coupling the first conductive plate to the second conductive plate; and a second via coupled to the first conductive plate. The first conductive plate includes a first portion coupled to the first via and the first conductive plate further includes a second portion coupled to the second via between the first portion and the component. The second via is coupled to either the second conductive plate or the third conductive plate.
Public/Granted literature
- US20190098855A1 APPARATUS AND METHODS FOR VIA CONNECTION WITH REDUCED VIA CURRENTS Public/Granted day:2019-04-04
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