Invention Grant
- Patent Title: Dynamic link error protection in memory systems
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Application No.: US15682533Application Date: 2017-08-21
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Publication No.: US10387242B2Publication Date: 2019-08-20
- Inventor: Jungwon Suh , Alain Artieri , Dexter Tamio Chun , Deepti Vijayalakshmi Sriramagiri
- Applicant: QUALCOMM Incorporated
- Applicant Address: US CA San Diego
- Assignee: QUALCOMM Incorporated
- Current Assignee: QUALCOMM Incorporated
- Current Assignee Address: US CA San Diego
- Agency: Muncy, Geissler, Olds & Lowe, P.C.
- Main IPC: G11C29/00
- IPC: G11C29/00 ; G06F11/10 ; G06F3/06

Abstract:
Errors can be introduced when data is transferred over a link between two entities such as between a host and a memory. Link error protection schemes can be implemented to detect and correct errors that occur on the link to enhance transmission reliability. However, these benefits are not without costs since such protection schemes increase both latency and power consumption. In one or more aspects, it is proposed to dynamically adjust the level of link error protection applied to match any change in the operating environment. For example, likelihood of link errors strongly correlates with the link speed. If the link speed is increased, a greater level of link error protection can be applied to counteract the increase in the link errors. If the link speed is decreased, the level of protection can be decreased so that latency and power consumption penalties can be minimized.
Public/Granted literature
- US20190056990A1 DYNAMIC LINK ERROR PROTECTION IN MEMORY SYSTEMS Public/Granted day:2019-02-21
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