Invention Grant
- Patent Title: Uniform electrochemical plating of metal onto arrays of pillars having different lateral densities and related technology
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Application No.: US15872845Application Date: 2018-01-16
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Publication No.: US10396052B2Publication Date: 2019-08-27
- Inventor: Jonathan S. Hacker
- Applicant: Micron Technology, Inc.
- Applicant Address: US ID Boise
- Assignee: Micron Technology, Inc.
- Current Assignee: Micron Technology, Inc.
- Current Assignee Address: US ID Boise
- Agency: Perkins Coie LLP
- Main IPC: H01L23/00
- IPC: H01L23/00 ; H01L25/065 ; H01L25/00 ; G06F17/50

Abstract:
A semiconductor die assembly in accordance with an embodiment of the present technology includes first and second semiconductor dies spaced apart from one another. The first semiconductor die has a major surface with non-overlapping first and second regions. The semiconductor die assembly further includes an array of first pillars extending heightwise from the first region of the major surface of the first semiconductor die toward the second semiconductor die. Similarly, the semiconductor die assembly includes an array of second pillars extending heightwise from the second region of the major surface of the first semiconductor die toward the second semiconductor die. The first and second pillars have different lateral densities and different average widths. The latter difference at least partially offsets an effect of the former difference on relative metal deposition rates of an electrochemical plating process used to form the first and second pillars.
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