- Patent Title: Methods of forming dislocation enhanced strain in NMOS structures
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Application No.: US14912594Application Date: 2013-09-26
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Publication No.: US10396201B2Publication Date: 2019-08-27
- Inventor: Michael Jackson , Anand Murthy , Glenn Glass , Saurabh Morarka , Chandra Mohapatra
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Schwabe, Williamson & Wyatt, P.C.
- International Application: PCT/US2013/061859 WO 20130926
- International Announcement: WO2015/047267 WO 20150402
- Main IPC: H01L29/06
- IPC: H01L29/06 ; H01L29/10 ; H01L29/32 ; H01L29/66 ; H01L29/78 ; H01L29/165

Abstract:
Methods of forming a strained channel device utilizing dislocations disposed in source/drain structures are described. Those methods and structures may include forming a thin silicon germanium material in a source/drain opening of a device comprising silicon, wherein multiple dislocations are formed in the silicon germanium material. A source/drain material may be formed on the thin silicon germanium material, wherein the dislocations induce a tensile strain in a channel region of the device.
Public/Granted literature
- US20160204256A1 METHODS OF FORMING DISLOCATION ENHANCED STRAIN IN NMOS STRUCTURES Public/Granted day:2016-07-14
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