- Patent Title: Systems and methods for reducing performance state change latency
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Application No.: US15849945Application Date: 2017-12-21
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Publication No.: US10402121B2Publication Date: 2019-09-03
- Inventor: Rakesh L. Notani , Robert E. Jeter
- Applicant: Apple Inc.
- Applicant Address: US CA Cupertino
- Assignee: Apple Inc.
- Current Assignee: Apple Inc.
- Current Assignee Address: US CA Cupertino
- Agency: Meyertons, Hood, Kivlin, Kowert & Goetzel, P.C.
- Main IPC: G06F3/06
- IPC: G06F3/06

Abstract:
A method and apparatus for performing performance state changes are disclosed. A power management circuit may be configured to receive requests for changes to first and second performance states for at least at least one memory of a plurality of memories. In response to a determination that a change to the first performance state is in progress, when the request to change to the second performance state is received, the power management controller may send a notification to a controller coupled to the memories. The controller may halt scheduling of memory interface calibration operations for the at least one memory based on the notification.
Public/Granted literature
- US20190196740A1 SYSTEMS AND METHODS FOR REDUCING PERFORMANCE STATE CHANGE LATENCY Public/Granted day:2019-06-27
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