- Patent Title: Organizing memory to optimize memory accesses of compressed data
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Application No.: US14925920Application Date: 2015-10-28
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Publication No.: US10402323B2Publication Date: 2019-09-03
- Inventor: Praveen Krishnamurthy , Peter B. Holmquist , Wishwesh Gandhi , Timothy Purcell , Karan Mehra , Lacky Shah
- Applicant: NVIDIA CORPORATION
- Applicant Address: US CA Santa Clara
- Assignee: NVIDIA CORPORATION
- Current Assignee: NVIDIA CORPORATION
- Current Assignee Address: US CA Santa Clara
- Agency: Artegis Law Group, LLP
- Main IPC: G06F12/08
- IPC: G06F12/08 ; G06F12/0802 ; G06F3/06

Abstract:
In one embodiment of the present invention a cache unit organizes data stored in an attached memory to optimize accesses to compressed data. In operation, the cache unit introduces a layer of indirection between a physical address associated with a memory access request and groups of blocks in the attached memory. The layer of indirection—virtual tiles—enables the cache unit to selectively store compressed data that would conventionally be stored in separate physical tiles included in a group of blocks in a single physical tile. Because the cache unit stores compressed data associated with multiple physical tiles in a single physical tile and, more specifically, in adjacent locations within the single physical tile, the cache unit coalesces the compressed data into contiguous blocks. Subsequently, upon performing a read operation, the cache unit may retrieve the compressed data conventionally associated with separate physical tiles in a single read operation.
Public/Granted literature
- US20170123977A1 Organizing Memory to Optimize Memory Accesses of Compressed Data Public/Granted day:2017-05-04
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