- 专利标题: Guard ring design enabling in-line testing of silicon bridges for semiconductor packages
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申请号: US15749465申请日: 2015-10-29
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公开(公告)号: US10418312B2公开(公告)日: 2019-09-17
- 发明人: Arnab Sarkar , Sujit Sharan , Dae-Woo Kim
- 申请人: Intel Corporation
- 申请人地址: US CA Santa Clara
- 专利权人: Intel Corporation
- 当前专利权人: Intel Corporation
- 当前专利权人地址: US CA Santa Clara
- 代理机构: Schwabe, Williamson & Wyatt, P.C.
- 国际申请: PCT/US2015/058072 WO 20151029
- 国际公布: WO2017/074391 WO 20170504
- 主分类号: H01L23/498
- IPC分类号: H01L23/498 ; H01L23/544 ; H01L21/66 ; H01L23/58 ; H01L25/065 ; H01L23/00 ; H01L25/18
摘要:
Guard ring designs enabling in-line testing of silicon bridges for semiconductor packages, and the resulting silicon bridges and semiconductor packages, are described. In an example, a semiconductor structure includes a substrate having an insulating layer disposed thereon. A metallization structure is disposed on the insulating layer. The metallization structure includes conductive routing disposed in a dielectric material stack. The semiconductor structure also includes a first metal guard ring disposed in the dielectric material stack and surrounding the conductive routing. The first metal guard ring includes a plurality of individual guard ring segments. The semiconductor structure also includes a second metal guard ring disposed in the dielectric material stack and surrounding the first metal guard ring. Electrical testing features are disposed in the dielectric material stack, between the first metal guard ring and the second metal guard ring.
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