- Patent Title: Method for fabricating air gap adjacent to two sides of bit line
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Application No.: US16029638Application Date: 2018-07-08
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Publication No.: US10418367B2Publication Date: 2019-09-17
- Inventor: Yi-Ching Chang , Feng-Yi Chang , Fu-Che Lee , Chieh-Te Chen
- Applicant: UNITED MICROELECTRONICS CORP. , Fujian Jinhua Integrated Circuit Co., Ltd.
- Applicant Address: TW Hsin-Chu CN Quanzhou, Fujian Province
- Assignee: UNITED MICROELECTRONICS CORP.,Fujian Jinhua Integrated Circuit Co., Ltd.
- Current Assignee: UNITED MICROELECTRONICS CORP.,Fujian Jinhua Integrated Circuit Co., Ltd.
- Current Assignee Address: TW Hsin-Chu CN Quanzhou, Fujian Province
- Agent Winston Hsu
- Priority: CN201710347829 20170517
- Main IPC: H01L21/768
- IPC: H01L21/768 ; H01L27/108

Abstract:
A method for fabricating semiconductor device includes the steps of: providing a substrate having a cell region and a peripheral region; forming a bit line structure on the cell region and a gate structure on the peripheral region; forming an interlayer dielectric (ILD) layer around the bit line structure and the gate structure; forming a conductive layer on the bit line structure; performing a first photo-etching process to remove part of the conductive layer for forming storage contacts adjacent two sides of the bit line structure and contact plugs adjacent to two sides of the gate structure; forming a first cap layer on the cell region and the peripheral region to cover the bit line structure and the gate structure; and performing a second photo-etching process to remove part of the first cap layer on the cell region.
Public/Granted literature
- US20180337186A1 METHOD FOR FABRICATING AIR GAP ADJACENT TO TWO SIDES OF BIT LINE Public/Granted day:2018-11-22
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