Invention Grant
- Patent Title: Integrated circuit chip with strained NMOS and PMOS transistors
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Application No.: US15976452Application Date: 2018-05-10
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Publication No.: US10418486B2Publication Date: 2019-09-17
- Inventor: Remy Berthelon , Francois Andrieu
- Applicant: STMicroelectronics (Crolles 2) SAS , Commissariat A L'Energie Atomique et aux Energies Alternatives
- Applicant Address: FR Crolles FR Paris
- Assignee: STMicroelectronics (Crolles 2) SAS,Commissariat A L'Energie Atomique et aux Energies Alternatives
- Current Assignee: STMicroelectronics (Crolles 2) SAS,Commissariat A L'Energie Atomique et aux Energies Alternatives
- Current Assignee Address: FR Crolles FR Paris
- Agency: Crowe & Dunlevy
- Priority: FR1754199 20170512
- Main IPC: H01L29/78
- IPC: H01L29/78 ; H01L21/8238 ; H01L21/84 ; H01L27/02 ; H01L27/12 ; H01L27/092 ; H01L21/762 ; H01L29/786
Abstract:
Longitudinal trenches extend between and on either side of first and second side-by-side strips. Transverse trenches extend from one edge to another edge of the first strip to define tensilely strained semiconductor slabs in the first strip, with the second strip including portions that are compressively strained in the longitudinal direction and/or tensilely strained in the transverse direction. In the first strip, N-channel MOS transistors are located inside and on top of the semiconductor slabs. In the second strip, P-channel MOS transistors are located inside and on top of the portions.
Public/Granted literature
- US20180331221A1 INTEGRATED CIRCUIT CHIP WITH STRAINED NMOS AND PMOS TRANSISTORS Public/Granted day:2018-11-15
Information query
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