- 专利标题: Reduced latency I/O in multi-actuator device
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申请号: US15962877申请日: 2018-04-25
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公开(公告)号: US10424328B1公开(公告)日: 2019-09-24
- 发明人: Mark A. Gaertner , Bruce Douglas Buch , Devon Dallmann , Andrew Michael Kowles
- 申请人: Seagate Technology LLC
- 申请人地址: US CA Cupertino
- 专利权人: SEAGATE TECHNOLOGY LLC
- 当前专利权人: SEAGATE TECHNOLOGY LLC
- 当前专利权人地址: US CA Cupertino
- 代理机构: Holzer Patel Drennan
- 主分类号: G11B5/48
- IPC分类号: G11B5/48 ; G11B5/58 ; G11B5/56 ; G11B5/54
摘要:
An exemplary data refresh method disclosed herein reading data into volatile memory from a first storage region using a read element controlled by a first actuator assembly and writing the data from the volatile memory to a second storage region using a write element controlled by a second actuator assembly, where the first actuator assembly and the second actuator assembly are configured to receive data from control circuitry via independent read/write communication channels.
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