- 专利标题: Matrix reduction for lithography simulation
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申请号: US14506644申请日: 2014-10-04
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公开(公告)号: US10430543B2公开(公告)日: 2019-10-01
- 发明人: Thomas Christopher Cecil
- 申请人: Synopsys, Inc.
- 申请人地址: US CA Mountain View
- 专利权人: Synopsys, Inc.
- 当前专利权人: Synopsys, Inc.
- 当前专利权人地址: US CA Mountain View
- 代理机构: Alston & Bird LLP
- 主分类号: G06F17/50
- IPC分类号: G06F17/50 ; G03F7/20
摘要:
A matrix is produced for a semiconductor design. Interactions between mask edges in forming semiconductor shapes are determined and a graph created that shows those interactions. The graph is then partitioned into groups using a coloring algorithm, with each group representing one or more non-interacting mask edges. A lithography simulation is performed for each group, with the edges of that group perturbed, but the edges of other groups unmoved. The partial derivatives are calculated for the edges of a group based on the simulation with those edges perturbed, and used to populate locations in a Jacobian matrix. The Jacobian matrix is then used to solve an Optical Proximity Correction (OPC) problem by finding a mask edge correction vector for a given wafer targeting error vector.
公开/授权文献
- US20160098511A1 MATRIX REDUCTION FOR LITHOGRAPHY SIMULATION 公开/授权日:2016-04-07
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