- 专利标题: Thermally enhanced semiconductor package having field effect transistors with back-gate feature
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申请号: US15652826申请日: 2017-07-18
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公开(公告)号: US10431523B2公开(公告)日: 2019-10-01
- 发明人: Julio C. Costa , George Maxim , Dirk Robert Walter Leipold , Baker Scott
- 申请人: Qorvo US, Inc.
- 申请人地址: US NC Greensboro
- 专利权人: Qorvo US, Inc.
- 当前专利权人: Qorvo US, Inc.
- 当前专利权人地址: US NC Greensboro
- 代理机构: Withrow & Terranova, P.L.L.C.
- 主分类号: H01L23/373
- IPC分类号: H01L23/373 ; H01L21/8234 ; H01L29/423 ; H01L23/535 ; H01L29/06 ; H01L29/786 ; H01L23/31 ; H01L23/498 ; H01L23/00 ; H01L21/762
摘要:
The present disclosure relates to a thermally enhanced semiconductor package having field effect transistors (FETs) with a back-gate feature. The thermally enhanced semiconductor package includes a first buried oxide (BOX) layer, a first epitaxial layer over the first BOX layer, a second BOX layer over the first epitaxial layer, a second epitaxial layer over the second BOX layer and having a source, a drain, and a channel between the source and the drain, a gate dielectric aligned over the channel, and a front-gate structure over the gate dielectric. Herein, a back-gate structure is formed in the first epitaxial layer and has a back-gate region aligned below the channel. A FET is formed by the front-gate structure, the source, the drain, the channel, and the back-gate structure.
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