Invention Grant
- Patent Title: Semiconductor device, layout pattern and method for manufacturing an integrated circuit
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Application No.: US15463105Application Date: 2017-03-20
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Publication No.: US10431541B2Publication Date: 2019-10-01
- Inventor: Jian-Hong Lin , Hsin-Chun Chang , Hui Lee , Yung-Sheng Huang , Yung-Huei Lee
- Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
- Applicant Address: TW Hsinchu
- Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
- Current Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
- Current Assignee Address: TW Hsinchu
- Agency: McClure, Qualey & Rodack, LLP
- Main IPC: G06F17/50
- IPC: G06F17/50 ; H01L27/02 ; H01L23/522 ; H01L23/528

Abstract:
A semiconductor device for fabricating an IC is provided. The semiconductor device includes an interconnect structure and a first conductive line. The interconnect structure is made of conductive material and includes a first interconnect portion and a second interconnect portion. The second interconnect portion is connected to a first end of the first interconnect portion, and a width of the second interconnect portion is less than a width of the first interconnect portion. The first conductive line is arranged over or below the first interconnect portion and providing an electrical connection between the interconnect structure and an electrical structure. A distance between the first conductive line and the first end is less than a distance between the first conductive line and a second end of the first interconnect portion which is opposite to the first end.
Public/Granted literature
- US20180269148A1 SEMICONDUCTOR DEVICE, LAYOUT PATTERN AND METHOD FOR MANUFACTURING AN INTEGRATED CIRCUIT Public/Granted day:2018-09-20
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