Invention Grant
- Patent Title: Techniques for non-volatile memory page retirement
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Application No.: US15394261Application Date: 2016-12-29
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Publication No.: US10437512B2Publication Date: 2019-10-08
- Inventor: Feng Zhu , Aliasgar S. Madraswala , Xin Guo
- Applicant: INTEL CORPORATION
- Applicant Address: US CA Santa Clara
- Assignee: INTEL CORPORATION
- Current Assignee: INTEL CORPORATION
- Current Assignee Address: US CA Santa Clara
- Main IPC: G06F3/06
- IPC: G06F3/06 ; G11C29/00 ; G11C7/14 ; G11C29/52

Abstract:
Examples herein include techniques for flash page retirement following one or more defects in nonvolatile memory. In some examples, a storage controller may retire a first logical page in response to a first read error, and write data to the one or more NVM devices in a program-erase (P/E) cycle without a dummy page being programmed or generated for the retired first logical page. The storage controller may further retire a second logical page in response to a second read error, wherein the first logical page has a higher order than the second logical page in a same physical memory page.
Public/Granted literature
- US20180189154A1 Techniques for Non-Volatile Memory Page Retirement Public/Granted day:2018-07-05
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