Invention Grant
- Patent Title: Logic encryption using on-chip memory cells
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Application No.: US15381222Application Date: 2016-12-16
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Publication No.: US10438022B2Publication Date: 2019-10-08
- Inventor: Vikas Chandra , Mudit Bhargava
- Applicant: ARM Limited
- Applicant Address: GB Cambridge
- Assignee: Arm Limited
- Current Assignee: Arm Limited
- Current Assignee Address: GB Cambridge
- Agency: Leveque IP Law, P.C.
- Main IPC: G06F21/00
- IPC: G06F21/00 ; G06F21/72 ; H04L9/00 ; H04L9/06 ; G06F21/75 ; G06F21/76 ; H03K19/177 ; G09C1/06

Abstract:
A protected circuit includes a logic circuit having one or more input nodes and one or more output nodes. The logic circuit has a network of logic elements and one or more logic encryption elements. A logic encryption element includes a memory cell, such as a correlated electron switch for example, coupled with a configurable sub-circuit that is configured by a value stored in the memory cell to encrypt a signal or a signal path. A mapping of values at the one or more input nodes to values at the one or more output nodes corresponds to a desired mapping when values stored in the one or more memory cells match component values of a prescribed key vector. The memory cells may be programmed after fabrication of the circuit.
Public/Granted literature
- US20180173899A1 LOGIC ENCRYPTION USING ON-CHIP MEMORY CELLS Public/Granted day:2018-06-21
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