A method for automated configuration of a tester equipped for testing a control unit. A first and second model of technical systems being executed in the tester. The execution of the models taking place periodically with defined sampling rates. An FPGA executes the first and/or the second model and a CPU executes the first or the second model. A first individual sampling rate is allocated for the first model and a second individual sampling rate is allocated for the second model. The first model is assigned for execution on either the CPU or the FPGA and the second model is assigned for execution on either the CPU or the FPGA. The tester is automatically configured for execution of the first model with the first allocated sampling rate on the FPGA or the CPU and of the second model with the second allocated sampling rate on the FPGA or the CPU.