Invention Grant
- Patent Title: Ordering instructions in a processing core instruction buffer
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Application No.: US15085243Application Date: 2016-03-30
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Publication No.: US10445091B1Publication Date: 2019-10-15
- Inventor: Brett S. Feero
- Applicant: Apple Inc.
- Applicant Address: US CA Cupertino
- Assignee: Apple Inc.
- Current Assignee: Apple Inc.
- Current Assignee Address: US CA Cupertino
- Agency: Meyertons, Hood, Kivlin, Kowert & Goetzel, P.C.
- Main IPC: G06F9/30
- IPC: G06F9/30 ; G06F12/0875

Abstract:
In an embodiment, an apparatus includes a first buffer, a second buffer, and a control circuit. The control circuit may be configured to receive a first plurality of instructions included in a program. The control circuit may also be configured to store each of the first plurality of instructions in an entry of a first number of entries in the first buffer, arranged in the first number of entries dependent upon a received order. The control circuit may be further configured to select a second plurality of instructions from the first buffer. The second plurality of instructions may be selected dependent upon a program order. The control circuit may be configured to store each of the second plurality of instructions in an entry of a second number of entries in the second buffer, arranged in the second number of entries dependent upon the program order.
Information query