Invention Grant
- Patent Title: Semiconductor device
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Application No.: US16169601Application Date: 2018-10-24
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Publication No.: US10446655B2Publication Date: 2019-10-15
- Inventor: Tetsuya Watanabe , Mitsuru Miyamori , Katsumi Tsuneno , Takashi Shimizu
- Applicant: Renesas Electronics Corporation
- Applicant Address: JP Tokyo
- Assignee: RENESAS ELECTRONICS CORPORATION
- Current Assignee: RENESAS ELECTRONICS CORPORATION
- Current Assignee Address: JP Tokyo
- Agency: McDermott Will & Emery LLP
- Priority: JP2014-169834 20140822
- Main IPC: H01L29/417
- IPC: H01L29/417 ; H01L29/78 ; H01L23/522 ; H01L29/06

Abstract:
The semiconductor device including: two fins having rectangular parallelepiped shapes arranged in parallel in X-direction; and a gate electrode arranged thereon via a gate insulating film and extending in Y-direction is configured as follows. First, a drain plug is provided over a drain region located on one side of the gate electrode and extending in Y-direction. Then, two source plugs are provided over a source region located on the other side of the gate electrode and extending in Y-direction. Also, the drain plug is arranged in a displaced manner so that its position in Y-direction may not overlap with the two source plugs. According to such a configuration, the gate-drain capacitance can be made smaller than the gate-source capacitance and a Miller effect-based circuit delay can be suppressed. Further, as compared with capacitance on the drain side, capacitance on the source side increases, thereby improving stability of circuit operation.
Public/Granted literature
- US20190067428A1 SEMICONDUCTOR DEVICE Public/Granted day:2019-02-28
Information query
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