An inverting reciprocal quantum logic (RQL) phase-mode D flip-flop accepts a data input and a logical clock input. The flip-flop includes a stacked Josephson junction and a comparator. The triggering or untriggering of the stacked Josephson junction by positive or negative single flux quantum (SFQ) pulses can switch a direction of DC bias current through a component of the comparator, such as an output Josephson junction, which can then either pass or suppress logical clock SFQ pulses. When so passed, the data input is captured to the output upon clocking the flip-flop via the provision of the logical clock SFQ pulses, e.g., as reciprocal pulse pairs.