Disclosed are techniques for implementing routing aware placement for an electronic design. These techniques identify a block having one or more first pins or interconnects to be inserted into a first layer corresponding to a first set of tracks and identify a second set of tracks on a second layer adjacent to the first layer. One or more candidate locations may be generated on the first layer for the block based in part or in whole upon the first set of tracks. The block may be inserted into a candidate location on the first layer based in part or in whole upon respective costs or routability of the one or more candidate locations with respect to the second set of tracks.