Invention Grant
- Patent Title: Power electronics package and method of manufacturing thereof
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Application No.: US15000257Application Date: 2016-01-19
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Publication No.: US10453786B2Publication Date: 2019-10-22
- Inventor: Arun Virupaksha Gowda , Paul Alan McConnelee , Nancy Cecelia Stoffel , Risto Ilkka Tuominen
- Applicant: General Electric Company
- Applicant Address: US NY Schenectady
- Assignee: General Electric Company
- Current Assignee: General Electric Company
- Current Assignee Address: US NY Schenectady
- Agency: Ziolkowski Patent Solutions Group, SC
- Main IPC: H01L23/00
- IPC: H01L23/00 ; H01L23/31 ; H01L23/055 ; H01L23/498 ; H01L21/48 ; H01L25/16 ; H01L23/04 ; H01L23/08 ; H01L23/15 ; H01L23/538 ; H01L25/10

Abstract:
An electronics package is disclosed herein that includes a glass substrate having an exterior portion surrounding an interior portion thereof, wherein the interior portion has a first thickness and the exterior portion has a second thickness larger than the first thickness. An adhesive layer is formed on a lower surface of the interior portion of the glass substrate. A semiconductor device having an upper surface is coupled to the adhesive layer, the semiconductor device having at least one contact pad disposed on the upper surface thereof. A first metallization layer is coupled to an upper surface of the glass substrate and extends through a first via formed through the first thickness of the glass substrate to couple with the at least one contact pad of the semiconductor device.
Public/Granted literature
- US20170207160A1 POWER ELECTRONICS PACKAGE AND METHOD OF MANUFACTURING THEREOF Public/Granted day:2017-07-20
Information query
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