Invention Grant
- Patent Title: Class D amplifier circuit
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Application No.: US15886103Application Date: 2018-02-01
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Publication No.: US10461714B2Publication Date: 2019-10-29
- Inventor: John Paul Lesso , Toru Ido
- Applicant: Cirrus Logic International Semiconductor Ltd.
- Applicant Address: US TX Austin
- Assignee: Cirrus Logic, Inc.
- Current Assignee: Cirrus Logic, Inc.
- Current Assignee Address: US TX Austin
- Agency: Jackson Walker L.L.P.
- Priority: GB1415328.2 20140829
- Main IPC: H03F1/34
- IPC: H03F1/34 ; H03G3/30 ; H03F3/217 ; H03F1/26 ; H03F1/32 ; H03F3/187 ; H03G7/00

Abstract:
This application relates to Class D amplifier circuits (200). A modulator (201) controls a Class D output stage (202) based on a modulator input signal (Dm) to generate an output signal (Vout) which is representative of an input signal (Din). An error block (205), which may comprise an ADC (207), generates an error signal (ε) from the output signal and the input signal. In various embodiments the extent to which the error signal (ε) contributes to the modulator input signal (Dm) is variable based on an indication of the amplitude of the input signal (Din). The error signal may be received at a first input (204) of a signal selector block (203). The input signal may be received at a second input (206) of the signal selector block (203). The signal selector block may be operable in first and second modes of operation, wherein in the first mode the modulator input signal is based at least in part on the error signal; and in the second mode the modulator input signal is based on the digital input signal and is independent of the error signal. The error signal can be used to reduce distortion at high signal levels but is not used at low signal levels and so the noise floor at low signal levels does not depend on the component of the error block (205).
Public/Granted literature
- US20180159490A1 CLASS D AMPLIFIER CIRCUIT Public/Granted day:2018-06-07
Information query
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