Invention Grant
- Patent Title: Debugging translation block and debugging architecture
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Application No.: US15591161Application Date: 2017-05-10
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Publication No.: US10474515B2Publication Date: 2019-11-12
- Inventor: Baraa Al-Dabagh , Dongsheng Bi , Roi Uziel
- Applicant: Intel IP Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Intel IP Corporation
- Current Assignee: Intel IP Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Viering, Jentschura & Partner MBB
- Main IPC: G06F11/00
- IPC: G06F11/00 ; G01R31/317

Abstract:
An electronic device includes one or more integrated circuits, a debugging translation block, and a bus connected to the one or more integrated circuits and the debugging translation block, the bus configured to provide a connection to one or more external devices, wherein the debugging translation block is configured to receive debugging commands from a testing host device via the bus, convert the debugging commands into debugging input data, and provide the debugging input data to a debugging state machine of a first integrated circuit of the one or more integrated circuits.
Public/Granted literature
- US20180328986A1 DEBUGGING TRANSLATION BLOCK AND DEBUGGING ARCHITECTURE Public/Granted day:2018-11-15
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