Invention Grant
- Patent Title: Power and performance sorting of microprocessors from first interconnect layer to wafer final test
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Application No.: US14017634Application Date: 2013-09-04
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Publication No.: US10474774B2Publication Date: 2019-11-12
- Inventor: Emrah Acar , Moyra K. McManus , Sani R. Nassif , Matthew J. Sullivan
- Applicant: International Business Machines Corporation
- Applicant Address: US NY Armonk
- Assignee: International Business Machines Corporation
- Current Assignee: International Business Machines Corporation
- Current Assignee Address: US NY Armonk
- Agency: Scully, Scott, Murphy & Presser, P.C.
- Agent Daniel Morris, Esq.
- Main IPC: G06F17/50
- IPC: G06F17/50

Abstract:
A system, method and computer program product for sorting Integrated Circuits (chips), particularly microprocessor chips, and particularly that predicts chip performance or power for sorting purposes. The system and method described herein uses a combination of performance-predicting parameters that are measured early in the process, and applies a unique method to project where the part, e.g., microprocessor IC, will eventually be sorted. Sorting includes classifying the IC product to a subset of a family of products with the product satisfying certain performance characteristics or specifications, in the early stages of manufacturing, e.g., before the end product is fully fabricated.
Public/Granted literature
- US20150066467A1 POWER AND PERFORMANCE SORTING OF MICROPROCESSORS FROM FIRST INTERCONNECT LAYER TO WAFER FINAL TEST Public/Granted day:2015-03-05
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