Invention Grant
- Patent Title: Non-volatile memory aware caching policies
-
Application No.: US16015880Application Date: 2018-06-22
-
Publication No.: US10496536B2Publication Date: 2019-12-03
- Inventor: Kshitij Doshi , Bhanu Shankar
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: INTEL CORPORATION
- Current Assignee: INTEL CORPORATION
- Current Assignee Address: US CA Santa Clara
- Agency: Schwabe, Williamson & Wyatt, P.C.
- Main IPC: G06F12/0897
- IPC: G06F12/0897 ; G06F12/0804 ; G06F12/084 ; G06F12/126 ; G06F12/0868 ; G06F12/0873

Abstract:
In embodiments, an apparatus may include a CC, and a LLC coupled to the CC, the CC to reserve a defined portion of the LLC where data objects whose home location is in a NVM are given placement priority. In embodiments, the apparatus may be further coupled to at least one lower level cache and a second LLC, wherein the CC may further identify modified data objects in the at least one lower level cache whose home location is in a second NVM, and in response to the identification, cause the modified data objects to be written from the lower level cache to the second LLC, the second LLC located in a same socket as the second NVM.
Public/Granted literature
- US10534710B2 Non-volatile memory aware caching policies Public/Granted day:2020-01-14
Information query
IPC分类: