- 专利标题: Merged pillar structures and method of generating layout diagram of same
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申请号: US15882188申请日: 2018-01-29
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公开(公告)号: US10515178B2公开(公告)日: 2019-12-24
- 发明人: Hiranmay Biswas , Chung-Hsing Wang , Kuo-Nan Yang , Yi-Kan Cheng
- 申请人: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
- 申请人地址: TW Hsinchu
- 专利权人: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
- 当前专利权人: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
- 当前专利权人地址: TW Hsinchu
- 代理机构: Hauptman Ham, LLP
- 主分类号: G06F17/50
- IPC分类号: G06F17/50 ; H01L27/02 ; H01L27/118
摘要:
A method (of generating a layout diagram of a conductive line structure includes: determining that a first set of first to fourth short pillar patterns (which represent portions of an M(i) layer of metallization and are located relative to a grid), violates a minimum transverse-routing (TVR) distance of alpha-direction-separation, wherein (1) the grid has orthogonal alpha and beta tracks, and (2) the short pillar patterns have long axes which are substantially co-track aligned with a first one of the alpha tracks and have a first distance (of alpha-direction-separation between immediately adjacent members of the first set) which is less than the TVR distance; and merging pairings of the first & second and third & fourth short pillar patterns into corresponding first and second medium pillar patterns which have a second distance of alpha-direction-separation therebetween; the second value being greater than the TVR distance.
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