Invention Grant
- Patent Title: Layout optimization of a main pattern and a cut pattern
-
Application No.: US15357716Application Date: 2016-11-21
-
Publication No.: US10528693B2Publication Date: 2020-01-07
- Inventor: Shih-Ming Chang , Kuei-Liang Lu
- Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicant Address: TW
- Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
- Current Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
- Current Assignee Address: TW
- Agency: Haynes and Boone, LLP
- Main IPC: G06F17/50
- IPC: G06F17/50 ; H01L23/52 ; H01L21/027 ; H01L27/02 ; H01L23/528 ; G03F1/00
Abstract:
An integrated circuit device includes first and second features, each including an end portion arranged along a common axis, and separated by a space. The end portion of the first feature includes a first indention adjacent to the space. The end portion of the second feature includes a first indention adjacent to the space, mirroring the first indention of the first feature about the space. The end portions are substantially similar in shape.
Public/Granted literature
- US20170124243A1 Layout Optimization of a Main Pattern and a Cut Pattern Public/Granted day:2017-05-04
Information query
