A resistance variable memory apparatus includes a memory cell array region and a peripheral region disposed along an edge of the memory cell region. The memory cell array region may have a plurality of memory banks each of which includes at least one memory block. The resistance variable memory apparatus may include a data transmission block transmitting data between the plurality of memory banks and the peripheral region. The data transmission block includes a plurality of lower global input/output lines shared by pairs of adjacent memory banks, a plurality of lower multiplexers receiving data from pairs of adjacent lower global input/output lines and outputting data inputted from one of the lower global input/output lines, and an upper multiplexer receiving data output from the plurality of lower multiplexers and outputting data input from one of the lower multiplexers.