Invention Grant
- Patent Title: Fin patterning methods for increased process margins
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Application No.: US15684282Application Date: 2017-08-23
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Publication No.: US10535520B2Publication Date: 2020-01-14
- Inventor: Chin-Yuan Tseng , Wei-Liang Lin , Li-Te Lin , Ru-Gun Liu , Min Cao
- Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
- Applicant Address: TW Hsinchu
- Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
- Current Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
- Current Assignee Address: TW Hsinchu
- Agency: Haynes and Boone, LLP
- Main IPC: H01L21/033
- IPC: H01L21/033 ; H01L21/308 ; H01L21/8234 ; H01L21/8238 ; H01L29/417 ; H01L29/66

Abstract:
The present disclosure provides a method in accordance with some embodiments. The method includes forming a material layer that includes an array of fin features, wherein at least one fin feature has a first material on a first sidewall and a second material on a second sidewall that is opposite to the first sidewall, wherein the first material is different from the second material. The method further includes exposing the second sidewall of the at least one fin feature and removing the at least one fin feature.
Public/Granted literature
- US20180315602A1 Fin Patterning Methods for Increased Process Margins Public/Granted day:2018-11-01
Information query
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