A power on reset circuit includes a bias current generation module for generating a bias current, a power on reset module for generating a power on reset voltage signal, and a feedback latch module, which are electrically connected in sequence. The power on reset module includes two series switches capable of being turned on or off to adjust the bias current to further adjust the power on reset time. The feedback latch module is used for latching the power on reset voltage signal to restrain the jitter of the power voltage within the input voltage range VIL-VIH of inverters in the power on stage and to avoid jump of the signal. The feedback latch module comprises a feedback branch, which is formed by two NMOS transistors in series connection and achieves rapider and stable output of the power on reset voltage signal through feedback of the signal.