A processor includes a plurality of first processing units. A direct memory access unit is coupled to at least one first processing unit of the plurality of first processing units. The processor includes a plurality of data storage units. A second processing unit is adapted to process data from at least one data storage unit of the plurality of data storage units. The direct memory access unit is configured to transfer data stored in a memory to the at least one data storage unit of the plurality of data storage units. The second processing unit is separate from the plurality of first processing units and the direct memory access unit. The at least one first processing unit and the second processing unit are configured to work in parallel. The processor further includes a first register. The second processing unit is configured to receive an operation signal from the first register.