Invention Grant
- Patent Title: System and method for substrate wafer back side and edge cross section seals
-
Application No.: US14988639Application Date: 2016-01-05
-
Publication No.: US10546750B2Publication Date: 2020-01-28
- Inventor: Hamilton Lu , The-Tu Chau , Kyle Terrill , Deva N. Pattanayak , Sharon Shi , Kuo-In Chen , Robert Xu
- Applicant: VISHAY-SILICONIX
- Applicant Address: US CA Santa Clara
- Assignee: Vishay-Siliconix
- Current Assignee: Vishay-Siliconix
- Current Assignee Address: US CA Santa Clara
- Main IPC: H01L21/20
- IPC: H01L21/20 ; H01L21/02 ; H01L21/22 ; H01L29/16 ; H01L29/36 ; H01L29/78

Abstract:
Systems and methods for substrate wafer back side and edge cross section seals. In accordance with a first method embodiment, a silicon wafer of a first conductivity type is accessed. An epitaxial layer of the first conductivity type is grown on a front surface of the silicon wafer. The epitaxial layer is implanted to form a region of an opposite conductivity type. The growing and implanting are repeated to form a vertical column of the opposite conductivity type. The wafer may also be implanted to form a region of the opposite conductivity type vertically aligned with the vertical column.
Public/Granted literature
- US20160225622A1 SYSTEM AND METHOD FOR SUBSTRATE WAFER BACK SIDE AND EDGE CROSS SECTION SEALS Public/Granted day:2016-08-04
Information query
IPC分类: