Invention Grant
- Patent Title: Self-aligned via below subtractively patterned interconnect
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Application No.: US16070172Application Date: 2016-03-30
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Publication No.: US10546772B2Publication Date: 2020-01-28
- Inventor: Manish Chandhok , Richard E. Schenker , Hui Jae Yoo , Kevin L. Lin , Jasmeet S. Chawla , Stephanie A. Bojarski , Satyarth Suri , Colin T. Carver , Sudipto Naskar
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Schwabe, Williamson & Wyatt, P.C.
- International Application: PCT/US2016/025074 WO 20160330
- International Announcement: WO2017/171760 WO 20171005
- Main IPC: H01L23/52
- IPC: H01L23/52 ; H01L21/768 ; H01L21/311 ; H01L23/522
Abstract:
A plurality of interconnect features are formed in an interconnect layer on a first insulating layer on a substrate. An opening in the first insulating layer is formed through at least one of the interconnect features. A gap fill layer is deposited in the opening.
Public/Granted literature
- US20190035677A1 SELF-ALIGNED VIA BELOW SUBTRACTIVELY PATTERNED INTERCONNECT Public/Granted day:2019-01-31
Information query
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