- Patent Title: Semiconductor device and semiconductor device fabrication method
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Application No.: US15919652Application Date: 2018-03-13
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Publication No.: US10546773B2Publication Date: 2020-01-28
- Inventor: Yasunori Uchino , Kenichi Watanabe
- Applicant: FUJITSU SEMICONDUCTOR LIMITED
- Applicant Address: JP Kanagawa
- Assignee: FUJITSU SEMICONDUCTOR LIMITED
- Current Assignee: FUJITSU SEMICONDUCTOR LIMITED
- Current Assignee Address: JP Kanagawa
- Agency: Westerman, Hattori, Daniels & Adrian, LLP
- Priority: JP2013-126269 20130617
- Main IPC: G06F17/50
- IPC: G06F17/50 ; H01L21/00 ; H01L23/00 ; H01L21/768 ; H01L23/48 ; H01L23/522 ; H01L23/528

Abstract:
A multilayer wiring in a semiconductor device includes a first lower wiring formed in a first insulating layer, a via which is formed in a second insulating layer over the first insulating layer and which is connected to the first lower wiring, and an upper wiring connected to the via. The upper wiring has an outer edge at which a nick portion is formed beside a portion of the upper wiring to which the via is connected. The formation of the nick portion at the outer edge of the upper wiring prevents the via from enlarging.
Public/Granted literature
- US20180204766A1 SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE FABRICATION METHOD Public/Granted day:2018-07-19
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