Invention Grant
- Patent Title: Method for fabricating stack die package
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Application No.: US15439817Application Date: 2017-02-22
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Publication No.: US10546840B2Publication Date: 2020-01-28
- Inventor: Kyle Terrill , Frank Kuo , Sen Mao
- Applicant: VISHAY-SILICONIX
- Applicant Address: US CA San Jose
- Assignee: Vishay Siliconix, LLC
- Current Assignee: Vishay Siliconix, LLC
- Current Assignee Address: US CA San Jose
- Main IPC: H01L25/07
- IPC: H01L25/07 ; H01L23/495 ; H01L23/00 ; H01L23/31 ; H01L21/48 ; H01L21/56 ; H01L23/498 ; H01L23/544

Abstract:
In one embodiment, a method can include coupling a gate and a source of a first die to a lead frame. The first die can include the gate and the source that are located on a first surface of the first die and a drain that is located on a second surface of the first die that is opposite the first surface. In addition, the method can include coupling a source of a second die to the drain of the first die. The second die can include a gate and the source that are located on a first surface of the second die and a drain that is located on a second surface of the second die that is opposite the first surface.
Public/Granted literature
- US20170162403A1 METHOD FOR FABRICATING STACK DIE PACKAGE Public/Granted day:2017-06-08
Information query
IPC分类: