Invention Grant
- Patent Title: Method and apparatus for partial cache line sparing
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Application No.: US15912450Application Date: 2018-03-05
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Publication No.: US10579464B2Publication Date: 2020-03-03
- Inventor: Debaleena Das , Rajat Agarwal , Brian S. Morris
- Applicant: INTEL CORPORATION
- Applicant Address: US CA Santa Clara
- Assignee: INTEL CORPORATION
- Current Assignee: INTEL CORPORATION
- Current Assignee Address: US CA Santa Clara
- Agency: Konrad Raynes Davda & Victor LLP
- Agent David W. Victor
- Main IPC: G06F11/07
- IPC: G06F11/07 ; G06F3/06 ; G06F11/10

Abstract:
Provided are an apparatus and method to store data from a cache line at locations having errors in a sparing directory. In response to a write operation having write data for locations in one of the cache lines, the write data for a location in the cache line having an error is written to an entry in a sparing directory including an address of the cache line.
Public/Granted literature
- US20180196709A1 METHOD AND APPARATUS FOR PARTIAL CACHE LINE SPARING Public/Granted day:2018-07-12
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