A vertical memory device includes a substrate with a cell array region, a word line contact region, and a peripheral circuit region, gate electrodes parallel to the substrate in the cell array and word line contact regions, the gate electrodes being stacked and spaced apart in a direction perpendicular to the substrate, a channel structure through the gate electrodes in the cell array region, the channel structure being electrically connected to the substrate, a dummy channel structure through the gate electrodes in the word line contact region, the dummy channel structure being spaced apart from the substrate, and a conductive line parallel to the substrate and electrically connected to a first gate electrode, the conductive line crossing at least a portion of an extension of the dummy channel structure in the perpendicular direction.