A variable resistance memory device includes first memory cells and second memory cells. The first memory cells are between first and second conductive lines, and at areas at which the first and second conductive lines overlap. The second memory cells are between the second and third conductive lines, and at areas at which the second and third conductive lines overlap. Each first memory cell includes a first variable resistance pattern and a first selection pattern. Each second memory cell includes a second variable resistance pattern and a second selection pattern. At least one of the second memory cells is shifted from a closest one of the first memory cells.