Invention Grant
- Patent Title: Architecture and instruction set for implementing advanced encryption standard (AES)
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Application No.: US15639983Application Date: 2017-06-30
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Publication No.: US10594475B2Publication Date: 2020-03-17
- Inventor: Shay Gueron , Wajdi K. Feghali , Vinodh Gopal
- Applicant: INTEL CORPORATION
- Applicant Address: US CA San Jose
- Assignee: INTEL CORPORATION
- Current Assignee: INTEL CORPORATION
- Current Assignee Address: US CA San Jose
- Agency: NDWE, LLP
- Main IPC: G06F21/00
- IPC: G06F21/00 ; H04L9/06 ; G06F9/30 ; G06F21/60 ; H04L9/14

Abstract:
A flexible aes instruction for a general purpose processor is provided that performs aes encryption or decryption using n rounds, where n includes the standard aes set of rounds {10, 12, 14}. A parameter is provided to allow the type of aes round to be selected, that is, whether it is a “last round”. In addition to standard aes, the flexible aes instruction allows an AES-like cipher with 20 rounds to be specified or a “one round” pass.
Public/Granted literature
- US20170310469A1 ARCHITECTURE AND INSTRUCTION SET FOR IMPLEMENTING ADVANCED ENCRYPTION STANDARD (AES) Public/Granted day:2017-10-26
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