Invention Grant
- Patent Title: Vias and conductive routing layers in semiconductor substrates
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Application No.: US15687636Application Date: 2017-08-28
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Publication No.: US10600689B2Publication Date: 2020-03-24
- Inventor: Kyle K. Kirby , Sarah A. Niroumand
- Applicant: Micron Technology, Inc.
- Applicant Address: US ID Boise
- Assignee: Micron Technology, Inc.
- Current Assignee: Micron Technology, Inc.
- Current Assignee Address: US ID Boise
- Agency: Perkins Coie LLP
- Main IPC: H01L21/768
- IPC: H01L21/768 ; H01L23/48 ; H01L23/00

Abstract:
Through vias and conductive routing layers in semiconductor substrates and associated methods of manufacturing are disclosed herein. In one embodiment, a method for processing a semiconductor substrate includes forming an aperture in a semiconductor substrate and through a dielectric on the semiconductor substrate. The aperture has a first end open at the dielectric and a second end opposite the first end. The method can also include forming a plurality of depressions in the dielectric, and simultaneously depositing a conductive material into the aperture and at least some of the depressions.
Public/Granted literature
- US20170372961A1 VIAS AND CONDUCTIVE ROUTING LAYERS IN SEMICONDUCTOR SUBSTRATES Public/Granted day:2017-12-28
Information query
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